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IRT Nanoelec News

Heterogeneous Integration with Collective Die-to-Wafer Hybrid and Fusion Bonding Demonstration

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EV Group, a core partner of Nanoelec consortium, successfully demonstrates end-to-end process flow for collective die-to-wafer bonding with sub-two-micron placement accuracy. This breakthrough represents an important milestone in accelerating the deployment of heterogeneous integration in next-generation 2.5D and 3D semiconductor packaging. Such technologies are requiered for leading-edge applications such as artificial intelligence, autonomous driving, augmented/virtual… Lire la suite » ... Read more »

Advance Chip Design Through Cutting-Edge 3D Packaging Technologies

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Intel Corporation announced (PRESS RELEASE | 2020.10.27) a new collaboration with CEA-Leti on advanced #3D and packaging technologies for processors to advance chip design. The research will focus on further reducing the size of computer chips, optimizing interconnection technologies between the different elements of #microprocessors, and on new bonding and stacking technologies for silicon #wafers,… Lire la suite » ... Read more »

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