GaN technology is gaining ground and concentrating the investment efforts of the largest players in the RF and Power electronics market. To confirm its performance, this technology requires advanced means of characterization. The SERMA Technologies laboratory with the Science and Surface, IRT Nanoelec and CEA Tech laboratories present different techniques allowing to characterize both the… Lire la suite » ... Read more »
IRT Nanoelec News
After recent demonstration, in the frame of Nanoelec, of a new, wireless system that offers increased safety, flexibility and productivity gains to the blasting market, CEA-Leti and Davey Bickford Enaex have extended their joint laboratory for three years to continue development of innovative radio-frequency communication systems that remotely control networks of high-tech wireless electronic detonators…. Lire la suite » ... Read more »
EV Group, a core partner of Nanoelec consortium, successfully demonstrates end-to-end process flow for collective die-to-wafer bonding with sub-two-micron placement accuracy. This breakthrough represents an important milestone in accelerating the deployment of heterogeneous integration in next-generation 2.5D and 3D semiconductor packaging. Such technologies are requiered for leading-edge applications such as artificial intelligence, autonomous driving, augmented/virtual… Lire la suite » ... Read more »
Carac’20
//Characterization of new electronic components is essential to their design and ultimately to ensure their reliability. The 7th edition of the Carac Symposium took place online on the IRT Nanoelec webinar platform gathering 50 attendees. This edition focused on the performance gains of the very large equipment available under the Nanoelec / Characterization program, at… Lire la suite » ... Read more »
Intel Corporation announced (PRESS RELEASE | 2020.10.27) a new collaboration with CEA-Leti on advanced #3D and packaging technologies for processors to advance chip design. The research will focus on further reducing the size of computer chips, optimizing interconnection technologies between the different elements of #microprocessors, and on new bonding and stacking technologies for silicon #wafers,… Lire la suite » ... Read more »