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IRT Nanoelec News

3D packaging: Achieving 3-layer stacking integration for future smart imagers

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This article focuses on the silicon technology developments done by CEA-Leti regarding wafer-to-wafer hybrid bonding and HD TSVs and it presents the recent demonstrations of 2-layer and 3-layer stacking integrations. These demonstrations, together with the work done by other partners of the IRT Smart Imager Program (STMicroelectronics, Siemens EDA, Prophesee, Lynred, Grenoble INP-UGA) on applications… Lire la suite » ... Read more »

Navigating the Eco-Design Paradox: Criteria and Methods for Sustainable Eco-Innovation Assessment in Early Development Stages

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This paper examines the growing importance of eco-innovation in aligning sustainability with technological development. It explores the ‘eco-design paradox’, which emphasizes the tension between the need for flexible design and the availability of data required for assessing environmental impacts during early innovation stages. This paradox presents a challenge: the lack of detailed data can have… Lire la suite » ... Read more »

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