Advance Chip Design Through Cutting-Edge 3D Packaging Technologies

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Intel Corporation announced (PRESS RELEASE | 2020.10.27) a new collaboration with CEA-Leti on advanced #3D and packaging technologies for processors to advance chip design. The research will focus on further reducing the size of computer chips, optimizing interconnection technologies between the different elements of #microprocessors, and on new bonding and stacking technologies for silicon #wafers, especially for making high performance computing (HPC) applications.

Intel and CEA-Leti share the vision that advanced 3D integration and packaging tehcnologies will strengthen IT solutions in the area of HPC. The collaboration will allow to continue to accelerate our heterogeneous integration roadmap thanks to our combined broad base og 3D technologies, said Severine Cheramy, 3D Business Developer at CEA-Leti and Director of 3D integration program at IRT Nanoelec.

Chiplet assembled on a silicon interposer Schematic diagram
of a heterogeneous assembly