“The SiPearl start-up is raising 90 million euros to speed up the marketing of a European microprocessor.” Such was the headline of the Usine nouvelle on April 5, 2023, echoing the start-up’s official announcement. SiPearl is building the world’s first low-consumption microprocessor specifically for high-performance computing and designed to operate with any third-party accelerator (GPU, AI, quantum). It aims to be the core of Europe’s supercomputers.
The SiPearl team (around Vincent Casillas) at work on the Nanoelec/Easytech project. © Sipearl
“Our ambition is to be the leading designer of high-end microprocessors in France and in Europe”, explains Vincent Casillas, SVP R&D Software at SiPearl. “With our Rhea microprocessor, we aim to contribute to Europe’s technological sovereignty in the critical fields of artificial intelligence, medical research, combating climate change and energy management.”
Under an Easytech contract in 2022, SiPearl and Grenoble INP-UGA developed advanced functionalities on RISC-V[1] coprocessors present in the Rhea chip designed for supercomputers and data centers. “These coprocessors will provide security and power supply management functions for the ARM Neoverse V1 computer cores”, says Vincent Casillas. “The main technological hurdle for this project was the fact that the chip itself was only at the design stage! But we could not afford to waste time because the advanced functionalities to be developed on these dedicated micro-controllers will have a significant impact on differentiation with respect to the offerings from the competition.”
At the end of the Easytech project, SiPearl had a solution for testing the Rhea bootload sequence[2] as well as the tools allowing automatic start-up and execution of unit and functional tests on the coprocessors. “This solution allows shorter iterations in the development phases, while ensuring the stability of the functionalities already developed and tested. Consequently, we speed up our technological development thanks to Easytech”, Vincent Casillas concludes.
[1] RISC-V is an Instruction Set Architecture (ISA) in the processor’s native language. There are various ISAs, but what makes RISC V specific is the that it is free for any user to use and develop.
[2] bootloader: minimum program enabling code to begin on a chip at start-up