IRT Nanoelec hosted the second RISC-V Meeting in Paris on October 1rst & 3, 2019.
RISC-V is a 32, 64, or 128 bit open source instruction set architecture (ISA). RISC-V specifications can be used freely for teaching, research, and commercial purposes. Over the past several years, RISC-V has stood out for its role in microprocessor cybersecurity. IRT Nanoelec became a member of the RISC-V Foundation in 2018 with the goal of developing new secure hardware architectures and prototyping them on RISC-V processors for IoT, embedded, and automated learning systems.
The second RISC-V Meeting was held at the Espace Van Gogh Auditorium in Paris. This two-day event, sponsored by Adacore, Rambus, and Hensoldt, covered the challenges and opportunities of the RISC-V open source architecture and provided opportunities for stakeholders from academia and industry to connect and lay the groundwork for potential joint R&D projects.
The first day of the meeting was devoted to two training courses on the foundations of RISC-V in terms of architecture and programming. Next came three workshops on open hardware, the value of RISC-V for safe, secure computing, and the latest research in modelling and simulation.
The second day began with a presentation of current research to develop high-performance solutions, work to improve hardware-software interfaces, and the implementation of formal verification methods.
The meeting was attended by nearly 120 members of the academic and industrial R&D communities and featured high-level international speakers from the RISC-V Foundation, UCLouvain, Vienna University of Technology, and other institutions invited by the organizing committee, whose members span education (Grenoble Institute of Technology, Grenoble-Alpes University, research (CEA, Inria), and industry (STMicroelectronics, Thales, Greenwaves, Wisekey, etc.).
This year’s RISC-V Meeting was a success, and IRT Nanoelec is already planning the third edition of this event for 2020.