IEDM is the premier annual event for microelectronic devices.
And IRT Nanoelec’s latest 3D integration research—on 3D-NoC performance—will be the subject of a guest paper at the “Circuit Device Interaction – 3D Systems, Enabling Technologies and Characterizations” session.
The paper, New Perspectives for Multicore Architectures using Advanced Technologies, was co-authored by F. Clermidy, P. Vivier, D. Dutoit, Y. Thonnart, J.L. Gonzales, J.P. Noël, B. Giraud, A. Lévisse, O. Billoint, and S. Thuriès.
Researchers from Leti, STMicroelectronics, and Mentor Graphics developed a 3D-NoC offering 20 times less power consumption and 20% to 40% higher speeds than current solutions. The advance, achieved under an IRT Nanoelec project, involved stacking two layers of 96-core 28 nm FDSOI CMOS circuits connected with an active 65 nm CMOS interposer. The cores are on the interposer, which also ensures communication between the cores, electrical conversion, and other functions. The cores are separated by just a few hundred microns; discrete components on electronic boards are separated by several centimeters.