By the end of March 2021, France organizes an international meeting for the RISC-V worldwide community, for the 3rd time. Some teams contributing to Nanoelec programs are more and more involved in worldwide collaborations on open standards for processors innovation . In this frame, Nanoelec is strongly supporting the workshop “RISC-V week” and CEA is member of the RISC-V International Association and joint, since 2021, the Open Hardware Group. 4 questions to Fabien Clermidy, Fabien Clermidy, Head of Computing Departement at CEA List & CEA representative at the OpenHW Group.
What is the interest to focus on open hardware and software for innovative architecture for Nanoelec?
Innovation is required to keep environmental sustainability of the digitalization and the trend for electronics devices everywhere. The challenge to address is to enable design of specialized integrated devices and embedded systems that are frugal in energy while mastering their development costs and time.
Open Hardware enabled by RISC-V ISA and Open Software like Linux are creating common homegrounds and strong references for some dedicated markets facilitating collaborations and over which real innovations can be developed and accurately evaluated. They are powerful enablers for Nanoelec.
RISC-V is presented as “paving the way for the next 50 years of computing design and innovation”. What are the expected breakthroughs?
One of the breakthrough enabled by RISC-V Open ISA and Open Hardware as a whole is the ability to design specialized High Performance Computing SoCs “correct by construction” , “Secured by design” and/or “trustworthy”.
RISC-V facilitates more transversal innovation at the SoC or platform level. This will have a strong impact on low-power consumption and security research for instance, two areas that essentially require cross-disciplinary approaches (analog design, digital design, software).
Open-source hardware and especially RISC-V opens a whole field to innovation: e.g. computing cores, micro-architecture, integration with caches and memory hierarchy, and accelerators.
Despite the end of Moore’s Law, computing power increase can be achieved through accelerators co-designed to serve the requirements of a given business software stack. Finally, it will lead to de-facto standards that will facilitate implementations by various players who have their independence of action at heart.
This will have a strong impact in computing and embedded systems where specialization is paramount, like embedded perception, AI for autonomous vehicles, cloud computing, and HPC.
Participating in Open Hardware Group task forces will also increase Nanoelec capacity and skills for designing new kinds of processors, systems and tools?
In 2020, CEA, in the frame of IRT Nanoelec, renewed its membership to RISC-V International, a Zürich-based foundation that drives collaboration around RISC-V ISA (Instruction Set Architectures) specifications. Joining the OpenHW Group, a forum dedicated to cooperation on the development of open-source cores, tools and software, allows us to go forward and collaborate on actual implementations.
Within the challenges of hardware designs are the costs and time required for the last stages of IP verification. It is important to catch bugs early on to reduce verification costs, and improve time-to-market. The openness of RISC-V ISA allows collaboration on verification tools, e.g. of ISA implementations. Open collaboration, massive reuse and sharing will quickly improve these IP and tools maturities.
The same kind of virtuous circle will come for other SoC technologies that will be open sourced, e.g. NoC, cache coherency, virtual memory, vector processing, or specialized processors based on RISC-V ISA extensions and accelerators.
The OpenHW Group, as a not-for-profit global organization, is also a tremendous opportunity to expose our contributions to potential partners on the global market.
By the end of March 2021, France organizes an international meeting for the RISC-V worldwide community, for the 3rd time. Let us know about the purpose of the meeting.
The proprietary nature of previous ISA left little possibilities, if at all, for collaboration between hardware and software research communities. With the advent RISC-V and open source hardware, it is important to bring together these two communities in order to co-optimize at the system level and fully realize the benefits of open source hardware and software. We can see the benefits of this approach in our own developments for security for IoT and variable precision floating-point in numerical computing.
The “3rd RISC-V Meeting” and the “OpenHW Day” will further emphasis the benefits of hardware and software co-design and open source collaboration. These events will be both online and, hopefully, IRL (in real life) in Palaiseau and Grenoble.
In addition to 20 technical presentations, we will have the pleasure to have significant contributions from prominent personalities of our community like Prof. Gernot Heiser (UNSW Sidney), Prof. Luca Benini (ETHZ & Univ. Bologna), PhD Rishiyur S. Nikhil (Bluespec), PhD Gabriel L. Somlo (CERT/SEI, CMU) and Dominic Rizzo (Google).
A wonderful program is waiting for us!! (see here)