RISC-V Summit Europe in Barcelona

Share on:

Contrary to the world’s most common instruction set architectures (ISA)[1], RISC-V is an open-source model[2]. This means that developers can fully access and modify the architecture, and use it for their own applications. CEA teams involved in Nanoelec will be at the annual European RISC-V[3] Summit in Barcelona, which runs from June 5-9, 2023. Before heading to Spain, Mikael Carmona, Head of Laboratory for Security of Hardware Components (CEA-Leti), talked to us about the challenges of this technology, poised to become a new standard.

Mikael Carmona, Head of Laboratory for Security of Hardware Components (CEA-Leti) (c) DR

What are the advantages of open-source materials and applications for innovative architecture?

By using an open-source instruction set architecture, or ISA, developers can build end-to-end processors since they have full control over material and application components. There are at least two advantages for innovation: first, it offers myriad possibilities to design new, technologically disruptive processors with high performance and security features. Second, part of the development can be shared with a community well beyond the project’s initiator. Sharing ensures faster and consolidated development of technology blocks without having to transfer intellectual property rights.

What role does RISC-V play in Nanoelec’s digital trust applications?

The goal of the Nanoelec/Pulse program is to make RISC-V ISA processors secure; open source ISAs are a means to ensure that their architecture is intrinsically secure. For processors based on a proprietary ISA, any detected vulnerability is fixed by adding a “patch”. This leads to a significant cost increase in surface (silica) and performance (time) due to the need for a solution that will directly modify the core and make it resilient.

How can RISC-V be an alternative to ARM processors, which are ubiquitous in mobile phones and tablets, and even in certain computers?

The RISC-V Foundation foresees over 80 million RISC-V cores in the automobile, IoT, and industrial markets by 2025. In 2022, ROMA, the first RISC-V laptop, arrived on the market, and Android was able to support RISC-V architecture. As a result, RISC-V has become a direct competitor of ARM in an ecosystem which is powerful (Google, IBM, Samsung) and dense (number of markets and company types).

Why is RISC-V not an issue in the trade war between the United States and China?

An ISA is not the only hardware component of a processor. Although there is no current fight for sovereignty over ISAs, the trade war has nevertheless affected electronic components. One of the goals of the Nanoelec/Pulse program is to design and characterize intrinsically secure RISC-V processors, and therefore gain a competitive edge over current security solutions.

What will the highlights of the 2023 RISC-V Summit Europe be?

In Barcelona, we will introduce two security innovations for RISC-V processors:

  • ScrambleCache is a highly effective technique to secure the cache of application processors. Safeguarding against cache-based attacks means, for example, protecting the data encryption key on a medical device processor to prevent theft of medical data.
  • The memory encryption engine (MEE) encrypts (confidentiality) and authenticates (integrity) data stored in DRAM (or Flash) memory, which then travels to lower-level caches to be executed by the processor. With an additional cost of only 10% on Linux execution latency and 3% on core area used, this innovation offers consistent protection against DRAMA and Rowhammer attacks, which can alter data stored in non-volatile memory and render systems unusable.


[1] An ISA defines the set of basic operations (representation and address mode of data types, registers, instructions) to execute computer programs (codes) via a processor.

[2] RISC-V stands for Reduced Instruction Set Computing Five, meaning it is a simplified (reduced) version of the set of instructions compared with older, more complex architectures. The term “Five” indicates the fifth version of the architecture.

[3] The RISC-V Summit Europe https://riscv-europe.org/