Large multi-core 3D systems with multiple chiplets integrated on an active silicon interposer to support High Performance Computing (HPC) applications

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Perceval Coudrain (CEA-Leti) who works on 3D integration and advanced encapsulation, in the frame of IRT Nanoelec, received the “Best Paper Award” at the ECTC conference (May 2019, Las Vegas, USA) for his article entitled “Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures”. The paper reports the first successful technological integration of chiplets on a fully processed, packaged and tested, active silicon interposer. Announced in January 2020, the prize will be officially awarded at the next IEEE ECTC conference.



At ISSCC 2020 conference, (Feb. 2020, San Francisco, USA), CEA teams reported a high-performance processor breakthrough reached in the frame of IRT Nanoelec. They implemented an active interposer as a modular and energy-efficient silicon platform that enables efficient integration of large-scale chiplet-based computing systems for high-performance computing (HPC) and big-data applications.