IRT Nanoelec attended the European 3D Summit held on the MINATEC campus in Grenoble on January 18–20.
Séverine Cheramy, who heads the 3D Integration program at IRT Nanoelec gave a plenary talk on the latest developments in very-early-stage technologies like copper-copper direct chip-to-chip bonding and 3D partitioning design techniques for circuits (using 3D approaches for circuit design).
IRT Nanoelec also exhibited at a booth shared with the CEA, showcasing the latest research coming out of the 3D Integration program, as well as the most recent results obtained on demonstrator systems. Visitors to the booth got to see a live simulation of a 3D Network-on-Chip demonstrator developed by IRT Nanoelec in operation; the demonstrator shows how the various components of the chip adjust their activity depending on the amount of heat the chip is generating.
IRT Nanoelec’s partners were also at the event, either exhibiting at their own booths or, for STMicroelectronics, SET, and Mentor Graphics, giving talks.
