In research conducted under the IRT Nanoelec 3D Integration program, design work on a circuit named INTACT has been completed. The 28 nm FDSOI circuit was sent to foundry based on STMicroelectronics’ multi-project technology roadmap.
The INTACT 3D circuit is made up of six 20 nm FDSOI circuits, each with sixteen 32-bit MIPS cores. The circuit offers a memory hierarchy with three coherent caches. The circuits are 3D-assembled on a 65 nm active interposer integrating communications, power management, and testing and troubleshooting (mechanical, thermal, etc.) functions. The 3D circuit was designed and validated using Mentor Graphics® tools and was made using 240 µm-pitch copper pillars and TSVs with a form factor of 10:1. The circuit boasts a total of 96 cores, with processing power of 96 GOPS and energy efficiency of 10 GOPS/W. This level of performance marks a world first, doubling performance and tripling complexity compared to the current state of the art. The circuit will go to fabrication in early 2016 for testing in the summer of 2016.