Trends like high-performance computing, big data, and new network architectures are creating a need for huge, yet highly-energy-efficient processing power. In research conducted under the IRT Nanoelec 3D Integration program, an integrated circuit and the associated application chip were developed.
The TSARLET circuit is built on a multi-core architecture with sixteen processor cores using coherent caches implemented on STMicroelectronics’ 28 nm FD-SOI platform.
The TSARLET circuit has been fabricated and tested. Measurement and implementation on an application chip are currently in progress. The circuit has been determined functional at more than 1 GHz over a wide range of voltages (0.5 V to 1.3 V); the 28 nm FD-SOI technology ensures polarization management. The circuit runs a Linux kernel on its sixteen cores on the dedicated application chip that includes a processing core and all peripherals.
The next steps will be to port the applications to the TSARLET circuit and its application chip and to prepare to manufacture the circuit. The results have been encouraging in the early stages in terms of an extended 3D version of the circuit, called INTACT. INTACT integrates six TSARLET circuits on an active interposer for a total of 96 cores distributed over six chiplets. The total processing capacity is more than 100 GOPS. Fabrication of the INTACT circuit is currently in progress.
