The paper “Packaging of high speed 100 Gbps silicon photonic photoreceiver module using 50 μm pitch microbump Flip-Chip and Chip-On-Board approach” co-authored by Olivier Castany, Benjamin Blampey, Benoit Charbonnier, Gabriel Pares, Maxime Germain, Isabelle Borel, Stephane Malhouitre, Christophe Kopp, and Stephane Bernabe (Grenoble Alpes University, CEA Leti); and Enrico Temporiti (STMicroelectronics) won the Best Paper Award at IEEE ESTC 2016 (Electronics System-Integration Technology Conference) held on September 13–15 at the Grenoble World Trade Center.
The award is one worth winning! More than 450 people attended the conference—Europe’s biggest packaging event (www.est2016.eu). It is also the first high-level packaging, 3D integration, and interconnect-community award bestowed upon research conducted under the IRT Nanoelec Silicon Photonics program.