This article focuses on the silicon technology developments done by CEALeti regarding wafer-to-wafer hybrid bonding and HD TSVs and it presents the recent demonstrations of 2-layer and 3-layer stacking integrations. These demonstrations, together with the work done by other partners of the IRT Smart Imager Program (STMicroelectronics, Siemens EDA, Prophesee, Lynred, Grenoble INP-UGA) on applications and architecture studies, design tools and methodologies, and neural networks optimizations, are key and pave the way for the next generation of smart imagers.
Chip Scale Review July-August 2024 (Volume 28, Number 4), “Achieving 3-layer stacking integration for future smart imagers”, Stephan Borel, Stéphane Nicolas
A lire en anglais.