RISC-V Europe Summit 2026

Nanoelec is partenering the RISC-V Europe Summit 2026, the premier event that connects the European movers and shakers – from industry, government, research, academia and ecosystem support – that are building the future of innovation on RISC-V.

Teams from CEA-Leti, Université Grenoble-Alpes and Mines Saint-Etienne supported by Nanoelec will present:

• an open-source framework that leverages both the Zfh (scalar float16) and the Zvfh (vector
  float16) extensions to enable complete on-device training on resource-constrained RISC-V single-core.
• A demonstrator for an Intrinsec Secured Processor

RISC-V is an open-source instruction set for processor architectures. Here are a few key points to help you understand what RISC-V is. RISC-V is often seen as a promising alternative to proprietary architectures, particularly in a context where open source and modularity are increasingly valued.