{"id":5242,"date":"2026-05-03T08:22:40","date_gmt":"2026-05-03T06:22:40","guid":{"rendered":"https:\/\/irtnanoelec.fr\/?post_type=actualite&p=5242"},"modified":"2026-05-19T22:04:56","modified_gmt":"2026-05-19T20:04:56","slug":"optimizing-performance-and-environmental-impact-the-challenge-of-3d-chips","status":"publish","type":"actualite","link":"https:\/\/irtnanoelec.fr\/en\/actualite\/optimizing-performance-and-environmental-impact-the-challenge-of-3d-chips\/","title":{"rendered":"Optimizing Performance and Environmental Impact: The Challenge of 3D Chips"},"content":{"rendered":"
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<\/span>Optimiser performance et impact environnemental, le d\u00e9fi des puces 3D<\/h2>

Pour d\u00e9velopper des capacit\u00e9s d\u2019\u00e9coconception des composants \u00e9lectroniques, le CEA et l\u2019IRT Nanoelec se dotent d\u2019outils d\u2019analyse de cycle de vie (ACV) et d\u2019impact environnemental. Leur tout premier mod\u00e8le appliqu\u00e9 aux architectures \u00e9lectroniques les plus avanc\u00e9es a \u00e9t\u00e9 pr\u00e9sent\u00e9 \u00e0 la conf\u00e9rence IEEE SusTech 2026 (<\/a>19-22 avril, 2026, California\/USA). Leurs premiers calculs d\u00e9montrent que les strat\u00e9gies d\u2019empilement des puces peuvent aider \u00e0 r\u00e9duire l\u2019impact environnemental des composants si elles aident \u00e0 d\u00e9velopper des composants plus compacts.<\/h3>\n

En micro\u00e9lectronique, la prise en compte de crit\u00e8res d\u2019impact environnemental, voire soci\u00e9tal, requiert l\u2019adaptation des proc\u00e9d\u00e9s de conception et de d\u00e9veloppement d\u2019un nouveau composant. La communaut\u00e9 scientifique cherche donc \u00e0 se doter d\u2019outils adapt\u00e9s, facilitant les analyses de cycle de vie (ACV) afin de syst\u00e9matiser et normaliser des m\u00e9thodes d\u2019\u00e9valuations d’impact d\u00e8s la phase de conception du composant.<\/p>\n

La d\u00e9marche est tr\u00e8s souvent difficile \u00e0 mettre en \u0153uvre en raison de lacunes ou d\u2019incertitudes dans les ensembles de donn\u00e9es indispensables \u00e0 l’inventaire du cycle de vie. La communaut\u00e9 scientifique manque aussi d’outils performants et norm\u00e9s pour les calculs et les comparaisons.<\/p>\n

\u00ab\u00a0Cette difficult\u00e9 est particuli\u00e8rement forte pour les composants int\u00e9grant des assemblages multipuces,<\/em> souligne Mathilde Billaud chercheuse CEA, co-autrice d\u2019un article pr\u00e9sent\u00e9 \u00e0 la conf\u00e9rence IEEE SusTech 2026[1]<\/a>. Aussi, pour aider \u00e0 concevoir des assemblages multipuces empil\u00e9es en 3D, avons-nous con\u00e7u et d\u00e9velopp\u00e9 un nouveau mod\u00e8le d’ACV in\u00e9dit qui ne n\u00e9cessite qu’un ensemble limit\u00e9 de param\u00e8tres de conception.\u00a0\u00bb<\/em><\/p>\n

Toute premi\u00e8re ACV comparative de trois architectures de capteurs d’image<\/h3>\n

Avec ce mod\u00e8le de calcul d’ACV, l\u2019\u00e9quipe du CEA, dans le cadre d\u2019un programme soutenu et financ\u00e9 par l\u2019IRT Nanoelec et le projet europ\u00e9en EECONE, publie la toute premi\u00e8re ACV comparative de trois architectures de capteurs d’image CMOS multicouches (CIS)[2]<\/a>. \u00ab Nos r\u00e9sultats montrent que les impacts environnementaux des CIS multicouches sont principalement li\u00e9s \u00e0 la fabrication des circuit CMOS. En outre, nous avons constat\u00e9 que le CIS le plus \u00e9conome en \u00e9nergie ne peut compenser ses impacts de fabrication plus importants qu’apr\u00e8s une longue p\u00e9riode d’utilisation du composant, <\/em>explique Maxime Peralta, chercheur CEA, premier auteur de la publication. On d\u00e9montre aussi que l’empilement d’une troisi\u00e8me couche de silicium peut r\u00e9duire les impacts de fabrication en r\u00e9duisant la taille de la puce. Ainsi la recherche d\u2019une architecture \u00e9lectronique plus compacte semble une voie vertueuse en termes d\u2019environnement.\u00a0\u00bb<\/em><\/p>\n

Open source<\/h3>\n

Le mod\u00e8le d’ACV propos\u00e9 et les donn\u00e9es environnementales d\u2019int\u00e9gration 3D sont publi\u00e9s en open source<\/em> afin de faciliter de futurs travaux et de contribuer \u00e0 diffuser largement ces m\u00e9thodes de prise en compte des impacts au-del\u00e0 de la figure de m\u00e9rite PPAC[3]<\/a>. La publication comprend les r\u00e9sultats ACV de trois briques technologiques n\u00e9cessaires \u00e0 l\u2019int\u00e9gration 3D (amincissement du wafer, collage hybride et TSV haute densit\u00e9).<\/p>\n

\u00ab\u00a0Notre mod\u00e8le montre que la fabrication de circuits CMOS est g\u00e9n\u00e9ralement la premi\u00e8re source d’impact, p\u00e9nalisant ainsi les grandes puces et l’empilement de couches suppl\u00e9mentaires de circuits, ce qui p\u00e9nalise \u00e9galement le rendement de fabrication,\u00a0\u00bb<\/em> poursuit Maxime Peralta. \u00ab\u00a0N\u00e9anmoins, l’empilement d’une troisi\u00e8me couche de silicium peut contribuer \u00e0 r\u00e9duire la surface totale de silicium et les impacts environnementaux de la fabrication. Les \u00e9tapes de fabrication suppl\u00e9mentaires requises pour les processus d’int\u00e9gration 3D entra\u00eenent des co\u00fbts environnementaux minimes.\u00a0\u00bb<\/em><\/p>\n

Acc\u00e9l\u00e9rer l\u2019estimation des impacts environnementaux<\/h3>\n

Ces conclusions confirment des \u00e9tudes pr\u00e9c\u00e9dentes, mais, pour la premi\u00e8re fois, elles reposent sur des r\u00e9sultats exp\u00e9rimentaux v\u00e9rifiables sur plusieurs indicateurs environnementaux. La partie CMOS \u00e9tant la plus impactante, des \u00e9tudes sp\u00e9cifiques d\u2019ACV pouss\u00e9es sont men\u00e9es en parall\u00e8le sur la fabrication de puces CMOS FD-SOI dans le cadre de la ligne pilote FAMES. Elles reposent sur la collecte d\u2019informations pr\u00e9cises sur les proc\u00e9d\u00e9s de r\u00e9alisation afin d\u2019identifier la contribution de chaque \u00e9tape de proc\u00e9d\u00e9 et de comparer des alternatives de fabrication.<\/p>\n

Une telle approche de mod\u00e9lisation peut d\u00e9sormais \u00eatre facilement utilis\u00e9 pour d\u00e9finir de nouveaux composants car elle ne n\u00e9cessite qu’un ensemble limit\u00e9 de param\u00e8tres de conception. \u00ab\u00a0Ainsi, nous acc\u00e9l\u00e9rons l\u2019estimation des impacts environnementaux des composants pendant la conception, ouvrant ainsi la porte \u00e0 des d\u00e9marches d\u2019\u00e9co-conception\u00a0\u00bb<\/em>, souligne Maxime Peralta.<\/p>\n

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[1]<\/a> PPAC, pour \u00ab\u00a0Power, Performance, Area & Cost\u00a0\u00bb est une figure de m\u00e9rite pour l\u2019optimisation de nouveaux composants \u00e9lectroniques, uniquement bas\u00e9e sur des crit\u00e8res technologiques.<\/p>\n

[2]<\/a> IEEE Conference on Technologies for Sustainability (SusTech 2026, 19-22 avril 2026, Californie\/USA)<\/p>\n

[3]<\/a> Les calculs sont r\u00e9alis\u00e9s pour trois CIS diff\u00e9rents d\u00e9crits dans la litt\u00e9rature.<\/p>\n

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\n Sustech 2026<\/a> <\/div>\n <\/div>\n \n \n <\/div>\n <\/div>\n <\/section>\n
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Les strat\u00e9gies d\u2019empilement des puces pourraient aider \u00e0 r\u00e9duire l\u2019impact environnemental des composants si elles aident \u00e0 d\u00e9velopper des composants plus compacts (c) CEA\/Barbier<\/p>\n<\/div> <\/div>\n \n \n <\/div>\n <\/div>\n <\/section>\n\n

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