{"id":2285,"date":"2023-05-30T17:09:00","date_gmt":"2023-05-30T15:09:00","guid":{"rendered":"https:\/\/irtnanoelec.fr\/?post_type=actualite&p=2285"},"modified":"2025-08-01T11:18:08","modified_gmt":"2025-08-01T09:18:08","slug":"risc-v-summit-europe-in-barcelona-2","status":"publish","type":"actualite","link":"https:\/\/irtnanoelec.fr\/en\/actualite\/risc-v-summit-europe-in-barcelona-2\/","title":{"rendered":"RISC-V Summit Europe in Barcelona"},"content":{"rendered":"
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Contrary to the world\u2019s most common instruction set architectures (ISA)[1], RISC-V is an open-source model[2]. This means that developers can fully access and modify the architecture, and use it for their own applications. CEA teams involved in Nanoelec will be at the annual European RISC-V[3]\u00a0Summit in Barcelona, which runs from June 5-9, 2023. Before heading to Spain, Mikael Carmona, Head of Laboratory for Security of Hardware Components (CEA-Leti), talked to us about the challenges of this technology, poised to become a new standard.<\/p>\n<\/div> <\/div>\n \n \n <\/div>\n <\/div>\n <\/section>\n\n\n

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Mikael Carmona, Head of Laboratory for Security of Hardware Components (CEA-Leti) (c) DR<\/div> <\/div>\n
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<\/span>What are the advantages of open-source materials and applications for innovative architecture?<\/h2>

By using an open-source instruction set architecture, or ISA, developers can build end-to-end processors since they have full control over material and application components. There are at least two advantages for innovation: first, it offers myriad possibilities to design new, technologically disruptive processors with high performance and security features. Second, part of the development can be shared with a community well beyond the project\u2019s initiator. Sharing ensures faster and consolidated development of technology blocks without having to transfer intellectual property rights.<\/p>\n

What role does RISC-V play in Nanoelec\u2019s digital trust applications?<\/h4>\n

The goal of the Nanoelec\/Pulse program is to make RISC-V ISA processors secure; open source ISAs are a means to ensure that their architecture is intrinsically secure. For processors based on a proprietary ISA, any detected vulnerability is fixed by adding a \u201cpatch\u201d. This leads to a significant cost increase in surface (silica) and performance (time) due to the need for a solution that will directly modify the core and make it resilient.<\/p>\n<\/div> <\/div>\n \n \n <\/div>\n <\/div>\n <\/section>\n\n\n

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<\/span>How can RISC-V be an alternative to ARM processors, which are ubiquitous in mobile phones and tablets, and even in certain computers?<\/h2>

The RISC-V Foundation foresees over 80 million RISC-V cores in the automobile, IoT, and industrial markets by 2025. In 2022, ROMA, the first RISC-V laptop, arrived on the market, and Android was able to support RISC-V architecture. As a result, RISC-V has become a direct competitor of ARM in an ecosystem which is powerful (Google, IBM, Samsung) and dense (number of markets and company types).<\/p>\n<\/div> <\/div>\n \n \n <\/div>\n <\/div>\n <\/section>\n\n\n

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<\/span>Why is RISC-V not an issue in the trade war between the United States and China?<\/h2>

An ISA is not the only hardware component of a processor. Although there is no current fight for sovereignty over ISAs, the trade war has nevertheless affected electronic components. One of the goals of the Nanoelec\/Pulse program is to design and characterize intrinsically secure RISC-V processors, and therefore gain a competitive edge over current security solutions.<\/p>\n<\/div> <\/div>\n \n \n <\/div>\n <\/div>\n <\/section>\n\n\n

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<\/span>What will the highlights of the 2023 RISC-V Summit Europe be?<\/h2>

In Barcelona, we will introduce two security innovations for RISC-V processors:<\/p>\n