IRT Nanoelec partners CEA-Leti, STMicroelectronics, and Mentor Graphics have created an innovative 3D chip called NoC3D. The chip was developed to show how 3D stacking can be used in systems-on-chip (SoC).
The NoC3D chip is based on a 2D chip that can be used for standalone applications, such as in a 3D stack containing several chips, with the goal of boosting a system’s processing performance. A prototype of the new Mentor Graphics® Calibre® thermal analysis tool was used to analyze and model simulated and measured thermal effects in the 3D chip at the heart of the demonstrator system that was built. “The technology developed for the demonstrator chip is easy to adapt and use for applications combining several technologies, such as RF transmitter-receivers and imagers, or for complex digital processing needs like programmable components and high-performance-computing,” said Severine Cheramy, who heads 3D research at IRT Nanoelec. “At the same time, we are developing a 3D technology with a finer pitch than the 3D demonstrator chip for higher 3D interconnect densities; we are also working on solutions for heat dissipation, temporary bonding, and mechanical constraint management.”
The 3D stacking technology offers promise for improving both performance and integration density while bypassing the need to move up to the next technology node. This would enable different technologies to be integrated and allow the use of smaller chips to improve modularity and boost yields. In traditional complex 2D systems-on-chip the technology node is determined by the most complex function on the chip; the reuse methodology is performed at the IP. A 3D system combines several technologies and the reuse methodology can be performed at elementary chip, or “chiplet” level.
Leti drew up the specifications for the chip and designed it with direct support from STMicroelectronics using an additional custom 3D design kit and 3D verification tools provided by Mentor Graphics. STMicroelectronics and Leti contributed the CMOS technology, the 3D technology, and the packaging, using a “via-middle” approach for the 65 nm CMOS technology. The test and demonstrator chip is the result of joint development work involving all three partners.
The results of the research were published in a paper accepted at the ISSCC’2016 (International Solid State Circuits Conference) to be held from January 31 to February 4, 2016 in San Francisco.
- Vivet, Y. Thonnart, R. Lemaire, E. Beigné, C. Bernard, F. Darve, D. Lattard, I. Miro Panades, C. Santos, F. Clermidy, S. Cheramy, F. Pétrot, E. Flamand, J. Michailos, “A 4x4x2 Homogeneous Scalable 3D Network-on-Chip Circuit with 326 MFlit/s 0.66 pJ/bit Robust and Fault Tolerant Asynchronous 3D links”, ISSCC’2016, San Francisco, Feb. 2016.