14/12/2021 - 3D interconnects compatible with foundry manufactoring lines

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The study on « 3D interconnection using copper direct hybrid bonding for GaN on silicon wafer » presented by a CEA-Leti team supported by Nanoelec was awarded as ‘Best Paper’ at the IEEE International 3D System Integration Conference (3DIC, November 21).

« We have developed a complete process flow for 3D interconnection which is targeted to be compatible with foundry production line, including innovative CMP processs specifically developed for the new Cu/SiO2 hybrid interface with GaN devices », explains Christophe Dubarry as first author of the paper.

« The process described in the paper is performed on the back side of CMOS wafer, after hybrid bonding on the wafer front side. The integration process maintained good metal integrity all along the 3D link despite the heterogeneous conductive materials. And our electrical test vehicle have shown excellent morphological and electrical performances (Resistance, and leakage) with connection dimensions ranging from 3×3 µm2 to 5×5 µm2 size which confirm the scalability of these 3D contacts », he comments.

Today a 3D functional interconnections process flow for GaN applications is under development with Cu/SiO2. Applications like 6G or displays could use these interconnections between a GaN device and logic devices on silicon.

  •  Christophe Dubarry & al. 3D interconnection using copper direct hybrid bonding for GaN on silicon wafer. 3DIC – 2021 Conference (IEEE International 3D System Integration Conference). Read here